Vendor: Timeplex
Module: STMIB
[Automatically extracted from oidview.com]
restSlotEntry OBJECT-TYPE SYNTAX RestSlotEntry ACCESS not-accessible STATUS mandatory DESCRIPTION " " INDEX { restSlotAddr } ::= { restSlotTable 1 }
restSlotEntry OBJECT-TYPE SYNTAX RestSlotEntry ACCESS not-accessible STATUS mandatory DESCRIPTION " " INDEX { restSlotAddr } ::= { restSlotTable 1 }
OID | Name | Sub children | Sub Nodes Total | Description |
---|---|---|---|---|
1.3.6.1.4.1.16.101.1.2.2.3.1.1 | restSlotAddr | 0 | 0 | None |
1.3.6.1.4.1.16.101.1.2.2.3.1.2 | restSlotModuleDiagnostics | 0 | 0 | Remove will free bus bandwidth used by the ports of the module, and set the module start mode in the configuration MIB to off. Ins… |
1.3.6.1.4.1.16.101.1.2.2.3.1.3 | restSlotModuleStatus | 0 | 0 | None |
1.3.6.1.4.1.16.101.1.2.2.3.1.4 | restSlotModuleFailureType | 0 | 0 | If module status is fail, indicates what type of failure occurred. notApplicable will be returned if the module status is not fail… |
1.3.6.1.4.1.16.101.1.2.2.3.1.5 | restSlotModuleCondition | 0 | 0 | None |
1.3.6.1.4.1.16.101.1.2.2.3.1.6 | restSlotSWModuleType | 0 | 0 | None |
1.3.6.1.4.1.16.101.1.2.2.3.1.7 | restSlotSWModuleSubType | 0 | 0 | All the subtypes are defined in recfSlotModuleSubType entry. |
1.3.6.1.4.1.16.101.1.2.2.3.1.8 | restSlotModuleIDFormat | 0 | 0 | None |
1.3.6.1.4.1.16.101.1.2.2.3.1.9 | restSlotHWModuleType | 0 | 0 | None |
1.3.6.1.4.1.16.101.1.2.2.3.1.10 | restSlotHWModuleSubType | 0 | 0 | All the subtypes are defined in recfSlotModuleSubType entry. |
1.3.6.1.4.1.16.101.1.2.2.3.1.11 | restSlotModuleAssemblyNum | 0 | 0 | None |
1.3.6.1.4.1.16.101.1.2.2.3.1.12 | restSlotModuleRevision | 0 | 0 | None |
1.3.6.1.4.1.16.101.1.2.2.3.1.13 | restSlotModuleSerialNum | 0 | 0 | None |
1.3.6.1.4.1.16.101.1.2.2.3.1.14 | restSlotModuleDateMade | 0 | 0 | None |
1.3.6.1.4.1.16.101.1.2.2.3.1.15 | restSlotActiveRedundantSlot | 0 | 0 | None |
1.3.6.1.4.1.16.101.1.2.2.3.1.16 | restSlotModuleSWRevision | 0 | 0 | None |
1.3.6.1.4.1.16.101.1.2.2.3.1.17 | restSlotStartupDiagResults | 0 | 0 | Each bit displays the result (pass/fail) of a startup diagnostic. The bit map for the first four bytes is defined in recfSlotModul… |
1.3.6.1.4.1.16.101.1.2.2.3.1.18 | restSlotBGDiagResults | 0 | 0 | Each bit displays the result (pass/fail) of a background diagnostic. The bit map for the first four bytes is defined in recfSlotMo… |
1.3.6.1.4.1.16.101.1.2.2.3.1.19 | restSlotNumActivePorts | 0 | 0 | INTRODUCED 2.0.0 Number of ports on this module that have a restPortStatus value of active. |
1.3.6.1.4.1.16.101.1.2.2.3.1.20 | restSlotNumNormalPorts | 0 | 0 | INTRODUCED 2.0.0 Number of ports on this module that have a restPortCondition value of normal. |