The total number of ingress receive frames that the MLC has received
from the hdlc controller for this specified channel number.
Parsed from file lport_hdlc.mib.txt
Company: None
Module: APPIAN-LPORT-HDLC-MIB
The total number of ingress receive frames that the MLC has received
from the hdlc controller for this specified channel number.
Parsed from file APPIAN-LPORT-HDLC-MIB.mib
Module: APPIAN-LPORT-HDLC-MIB
Vendor: Tecnopro SA
Module: APPIAN-LPORT-HDLC-MIB
[Automatically extracted from oidview.com]
acLogicalHdlcIngressRxFrames OBJECT-TYPE SYNTAX Counter64 MAX-ACCESS read-only STATUS current DESCRIPTION "The total number of ingress receive frames that the MLC has received from the hdlc controller for this specified channel number. " ::= { acLogicalHdlcEntry 16 }
acLogicalHdlcIngressRxFrames OBJECT-TYPE SYNTAX Counter64 MAX-ACCESS read-only STATUS current DESCRIPTION "The total number of ingress receive frames that the MLC has received from the hdlc controller for this specified channel number. " ::= { acLogicalHdlcEntry 16 }
OID | Name | Sub children | Sub Nodes Total | Description |
---|---|---|---|---|
1.3.6.1.4.1.2785.2.4.4.1.1.1 | acLogicalHdlcNodeId | 0 | 0 | The node id is the id for this specific node in the OSAP ring. |
1.3.6.1.4.1.2785.2.4.4.1.1.2 | acLogicalHdlcSlot | 0 | 0 | The slot number within the chassis where the stats reside. |
1.3.6.1.4.1.2785.2.4.4.1.1.3 | acLogicalHdlcType | 0 | 0 | The type of data stream that this hdlc channel is framing. The current options are DS1, DS3, or DCC. |
1.3.6.1.4.1.2785.2.4.4.1.1.4 | acLogicalHdlcIndex | 0 | 0 | The acLogicalHdlcIndex is the index for this table for the specified type. For DS1 and DS3, the index is the same as the index … |
1.3.6.1.4.1.2785.2.4.4.1.1.5 | acLogicalHdlcStatsReset | 0 | 0 | Setting this attribute to True(1) will force all statistics for this row to be cleared and set to zero (0) values. Used for deb… |
1.3.6.1.4.1.2785.2.4.4.1.1.6 | acLogicalHdlcRxFifoOverrun | 0 | 0 | The total number of receive FIFO overruns that occurred in the hdlc controller for this specified channel number. This error occ… |
1.3.6.1.4.1.2785.2.4.4.1.1.7 | acLogicalHdlcRxMaxPktLenViolation | 0 | 0 | The total number of receive max packet packet length violations that occurred in the hdcl controller for the specified channel nu… |
1.3.6.1.4.1.2785.2.4.4.1.1.8 | acLogicalHdlcRxFCSError | 0 | 0 | The total number of receive FCS errors that occurred in the hdlc controller for this specified channel number. The FCS error is g… |
1.3.6.1.4.1.2785.2.4.4.1.1.9 | acLogicalHdlcRxNonOctetAligned | 0 | 0 | The total number of receive non-octet aligned errors that occurred in the hdlc controller for this specified channel number. Thi… |
1.3.6.1.4.1.2785.2.4.4.1.1.10 | acLogicalHdlcRxHdlcPktAbort | 0 | 0 | The total number of receive hdlc abort errors that occurred in the hdlc controller for this specified channel number. This error… |
1.3.6.1.4.1.2785.2.4.4.1.1.11 | acLogicalHdlcRxBufferStarvation | 0 | 0 | The total number of receive buffer starvation errors that occurred in the hdlc controller for this specified channel number. |
1.3.6.1.4.1.2785.2.4.4.1.1.12 | acLogicalHdlcTxFifoUnderrun | 0 | 0 | The total number of transmit FIFO underrun errors that occurred in the hdlc controller for this specified channel number. This e… |
1.3.6.1.4.1.2785.2.4.4.1.1.13 | acLogicalHdlcRxBundleDiscardDupSeq | 0 | 0 | The total number of receive bundle discard duplicate sequence errors that occurred in the hdlc controller for this specified cha… |
1.3.6.1.4.1.2785.2.4.4.1.1.14 | acLogicalHdlcRxBundleDiscardMissSeq | 0 | 0 | The total number of receive bundle discard missed sequence errors that occurred in the hdlc controller for this specified channe… |
1.3.6.1.4.1.2785.2.4.4.1.1.15 | acLogicalHdlcRxBundleDiscardQDepth | 0 | 0 | The total number of receive bundle discard queue depth errors that occurred in the hdlc controller for this specified channel nu… |
1.3.6.1.4.1.2785.2.4.4.1.1.17 | acLogicalHdlcEgressTxFrames | 0 | 0 | The total number of egress transmit frames that the MLC has transmitted to the hdlc controller for this specified channel number. |