A cpdbCardTable entry containing information
about a specific Cell Processor Daughter Board.
Parsed from file dl3200_.mib.txt
Company: diglink
Module: DL3200-MIB
Vendor: Digital-Link
Module: DL3200-MIB (dl3200_.mib)
Type: ENTRY
Access: not-accessible
Syntax: CpdbCardEntry
Automatically extracted from www.mibdepot.com
cpdbCardEntry OBJECT-TYPE SYNTAX CpdbCardEntry ACCESS not-accessible STATUS mandatory DESCRIPTION "A cpdbCardTable entry containing information about a specific Cell Processor Daughter Board." INDEX { cpdbCardIndex } ::= { cpdbCardTable 1 }
| OID | Name | Sub children | Sub Nodes Total | Description |
|---|---|---|---|---|
| 1.3.6.1.4.1.300.3.3.1.1.1 | cpdbCardIndex | 0 | 0 | The index of this card in the cpdbCardTable. |
| 1.3.6.1.4.1.300.3.3.1.1.2 | cpdbCardSlot | 0 | 0 | The index of the slot this card is in, in the slotTable. |
| 1.3.6.1.4.1.300.3.3.1.1.3 | cpdbDeviceName | 0 | 0 | A descriptive name that identifies the DTE card. Optional, but usage is recommended to aid management. |
| 1.3.6.1.4.1.300.3.3.1.1.4 | cpdbHwRev | 0 | 0 | The Cell Processor Daughter Board hardware revision. |
| 1.3.6.1.4.1.300.3.3.1.1.5 | cpdbInService | 0 | 0 | In-Service flag for Cell Processor Daughter Board. |
| 1.3.6.1.4.1.300.3.3.1.1.6 | cpdbInterface | 0 | 0 | Interface type for Cell Processor Daughter Board. |
| 1.3.6.1.4.1.300.3.3.1.1.7 | cpdbTdClkSCTE | 0 | 0 | Transmit Clock source for Cell Processor Daughter Board. |
| 1.3.6.1.4.1.300.3.3.1.1.8 | cpdbTdClkInv | 0 | 0 | Transmit Clock Inversion for Cell Processor Daughter Board. |
| 1.3.6.1.4.1.300.3.3.1.1.9 | cpdbTdClkGap | 0 | 0 | Use a Gapped Transmit Clock for Cell Processor Daughter Board. |
| 1.3.6.1.4.1.300.3.3.1.1.10 | cpdbDataRate | 0 | 0 | DTE Data Rate for Cell Processor Daughter Board. |
| 1.3.6.1.4.1.300.3.3.1.1.11 | cpdbOpMode | 0 | 0 | Operating Mode for Cell Processor Daughter Board. |
| 1.3.6.1.4.1.300.3.3.1.1.12 | lmiReporting | 0 | 0 | This parameter will enable or disable the response to DXI LMI reporting. |
| 1.3.6.1.4.1.300.3.3.1.1.13 | cpdbDSUtoDSUmode | 0 | 0 | DSUtoDSU Mode for Cell Processor Daughter Board. This will cause L3PDU packets to be processed one at a time, used when two DSU's… |
| 1.3.6.1.4.1.300.3.3.1.1.14 | cpdbHeartbeat | 0 | 0 | This parameter will enable or disable the response to DXI3.2 heartbeat poll test messsages when the E3 signal is bad. |
| 1.3.6.1.4.1.300.3.3.1.1.15 | cpdbPipelineMode | 0 | 0 | Pipeline Mode for Cell Processor Daughter Board, for minimum delay in the transmit direction. |
| 1.3.6.1.4.1.300.3.3.1.1.16 | cpdbSMDSdest | 0 | 0 | SMDS Destination address for Cell Processor DaughterBoard. This is expressed as ASCII characters which represent a 64-bit value. |
| 1.3.6.1.4.1.300.3.3.1.1.17 | cpdbSMDSsource | 0 | 0 | SMDS Source address for Cell Processor DaughterBoard. This is expressed as ASCII characters which represent a 64-bit value. |
| 1.3.6.1.4.1.300.3.3.1.1.18 | cpdbReassTimer | 0 | 0 | Reassambly Timer for Cell Processor Daughter Board, value expressed in milliseconds. |
| 1.3.6.1.4.1.300.3.3.1.1.19 | cpdbAccessClass | 0 | 0 | SMDS Access Class for Cell Processor Daughter Board. |
| 1.3.6.1.4.1.300.3.3.1.1.20 | cpdbTestLoop | 0 | 0 | This parameter specifies the Loopback test mode of the Cell Processor Daughter Board. |
| 1.3.6.1.4.1.300.3.3.1.1.21 | cpdbHwLoopEnable | 0 | 0 | This parameter will enable or disable the control of loopback test modes via the hardware interface. |
| 1.3.6.1.4.1.300.3.3.1.1.22 | cpdbTestMID | 0 | 0 | This parameter specifies the test MID value of the Cell Processor Daughter Board. |
| 1.3.6.1.4.1.300.3.3.1.1.23 | cpdbTxOver | 0 | 0 | This parameter enables the test ThruMode of the Cell Processor Daughter Board. |
| 1.3.6.1.4.1.300.3.3.1.1.24 | cpdbThruMode | 0 | 0 | This parameter enables the test ThruMode of the Cell Processor Daughter Board. |
| 1.3.6.1.4.1.300.3.3.1.1.25 | cpdbPktsTest | 0 | 0 | This parameter enables the L3 Packet Generating Test on the Cell Processor Daughter Board. |
| 1.3.6.1.4.1.300.3.3.1.1.26 | cpdbtxGenDa | 0 | 0 | SMDS Destination address for Cell Processor Daughter Board's Packet Test mode. This is expressed as ASCII characters which repres… |
| 1.3.6.1.4.1.300.3.3.1.1.27 | cpdbtxGenSa | 0 | 0 | SMDS Destination address for Cell Processor Daughter Board's Packet Test mode. This is expressed as ASCII characters which repres… |
| 1.3.6.1.4.1.300.3.3.1.1.28 | cpdbtxGenBytes | 0 | 0 | This parameter describes the number of bytes per packet for the Packets Test mode of the Cell Processor Daughter Board. |
| 1.3.6.1.4.1.300.3.3.1.1.29 | cpdbtxGenMsgDelay | 0 | 0 | This parameter describes the delay between packets for the Packets Test mode of the Cell Processor Daughter Board. |
| 1.3.6.1.4.1.300.3.3.1.1.30 | cpdbClearCounts | 0 | 0 | This parameter clears all counters of the Cell Processor Daughter Board. |
| 1.3.6.1.4.1.300.3.3.1.1.31 | cpdbCEXAtmVci | 0 | 0 | This parameter will be used for transmit VPI/VCI in CEX - ATM mode. |