This setting determines how interleaving is configured
for the ADI 918 chipset (bit 20 of Utopia register).
Parsed from file USR-CHIPSET-MIB.mib.txt
Company: None
Module: USR-CHIPSET-MIB
This setting determines how interleaving is configured
for the ADI 918 chipset (bit 20 of Utopia register).
Parsed from file USR-CHIPSET-MIB.mib
Module: USR-CHIPSET-MIB
Vendor: UTStarcom Incorporated
Module: USR-CHIPSET-MIB
[Automatically extracted from oidview.com]
adi918Interleaving OBJECT-TYPE SYNTAX INTEGER { off(1), on(2) } MAX-ACCESS read-write STATUS current DESCRIPTION "This setting determines how interleaving is configured for the ADI 918 chipset (bit 20 of Utopia register)." DEFVAL{ 2 } ::= { usrADI 1 }
adi918Interleaving OBJECT-TYPE SYNTAX INTEGER { off(1), on(2) } MAX-ACCESS read-write STATUS current DESCRIPTION "This setting determines how interleaving is configured for the ADI 918 chipset (bit 20 of Utopia register)." DEFVAL{ 2 } ::= { usrADI 1 }
| OID | Name | Sub children | Sub Nodes Total | Description |
|---|---|---|---|---|
| 1.3.6.1.4.1.429.4.33.1.0 | adi918Interleaving | 0 | 0 | None |
| OID | Name | Sub children | Sub Nodes Total | Description |
|---|---|---|---|---|
| 1.3.6.1.4.1.429.4.33.2 | adiOptionsSettings | 1 | 1 | This value is written to the OPTN.options register of the 910/918 chipset. |
| 1.3.6.1.4.1.429.4.33.3 | adiPSDMSettings | 1 | 1 | Setting for the PSDM.config register. |
| 1.3.6.1.4.1.429.4.33.4 | adiActualPSDMSettings | 1 | 1 | Setting for the PSDM.actual register. |
| 1.3.6.1.4.1.429.4.33.5 | adiGLiteFlag | 1 | 1 | This setting controls what Standards we are in, G. Lite or full rate T1.413, G.Dmt, or Multimode modes . |
| 1.3.6.1.4.1.429.4.33.6 | adiManualRetrain | 1 | 1 | Force manual retrain in G-Lite mode |
| 1.3.6.1.4.1.429.4.33.7 | adiClearProfiles | 1 | 1 | Clear profiles in G-Lite mode |
| 1.3.6.1.4.1.429.4.33.8 | adiUtopiaSetting | 1 | 1 | This value is written to the Utopia register of the 918 chipset. |
| 1.3.6.1.4.1.429.4.33.9 | adiEocFlag | 1 | 1 | This flag controls whether or not EOC processing is enabled. |
| 1.3.6.1.4.1.429.4.33.10 | adiPFCL1Settings | 1 | 1 | This value is written to the PFCL 1 register of the 910/918 chipset. |
| 1.3.6.1.4.1.429.4.33.11 | adiOPT4Settings | 1 | 1 | This value is written to the OPTN 4 register of the 918 chipset. |
| 1.3.6.1.4.1.429.4.33.12 | adiOPT5Settings | 1 | 1 | This value is written to the OPTN 5 register of the 918 chipset. |