Clock-normal samples data with the rising edge of the
selected tx clock, clock-invert samples data with the
falling edge of the selected tx clock. The tx clock is
selected using CfgDteTiming. This clock invertion is
most useful when loop-2 timing is used. Only in rare
circumstances will clock-invert (2) be used with loop-1
timing.
Parsed from file tylink-3250.mib.txt
Company: None
Module: TY3250I-MIB
Clock-normal samples data with the rising edge of the
selected tx clock, clock-invert samples data with the
falling edge of the selected tx clock. The tx clock is
selected using CfgDteTiming. This clock invertion is
most useful when loop-2 timing is used. Only in rare
circumstances will clock-invert (2) be used with loop-1
timing.
Parsed from file TY3250I-MIB.mib
Module: TY3250I-MIB
Vendor: Tylink
Module: TY3250I-MIB
[Automatically extracted from oidview.com]
ty3250CfgDteClockMode OBJECT-TYPE SYNTAX INTEGER { clock-normal (1), clock-invert (2) } ACCESS read-write STATUS mandatory DESCRIPTION "Clock-normal samples data with the rising edge of the selected tx clock, clock-invert samples data with the falling edge of the selected tx clock. The tx clock is selected using CfgDteTiming. This clock invertion is most useful when loop-2 timing is used. Only in rare circumstances will clock-invert (2) be used with loop-1 timing." ::= { ty3250CfgDteTable 4 }
ty3250CfgDteClockMode OBJECT-TYPE SYNTAX INTEGER { clock-normal (1), clock-invert (2) } ACCESS read-write STATUS mandatory DESCRIPTION "Clock-normal samples data with the rising edge of the selected tx clock, clock-invert samples data with the falling edge of the selected tx clock. The tx clock is selected using CfgDteTiming. This clock invertion is most useful when loop-2 timing is used. Only in rare circumstances will clock-invert (2) be used with loop-1 timing." ::= { ty3250CfgDteTable 4 }
OID | Name | Sub children | Sub Nodes Total | Description |
---|---|---|---|---|
1.3.6.1.4.1.466.4.4.4.0 | ty3250CfgDteClockMode | 0 | 0 | None |
OID | Name | Sub children | Sub Nodes Total | Description |
---|---|---|---|---|
1.3.6.1.4.1.466.4.4.1 | ty3250CfgDteLineRate | 1 | 1 | Serial Data Rate in bits-per-second, must be multiple of 8000bps. For example enter 768000 for 768Kb/s. Valid rates depend upon c… |
1.3.6.1.4.1.466.4.4.2 | ty3250CfgDteChannelDensity | 1 | 1 | Packing of serial data into T1 DS0's. Bit-7-stuff (56) allows DTE rates of nX56Kb/s and provides sufficient ones-density on any c… |
1.3.6.1.4.1.466.4.4.3 | ty3250CfgDteTiming | 1 | 1 | Serial DTE Transmit Timing mode. Loop-1 (1) uses the clock returned from the DTE (TT/TCE) to sample tx data, Loop-2 (2) uses the … |
1.3.6.1.4.1.466.4.4.5 | ty3250CfgDteDataMode | 1 | 1 | Inverts data. Can make some applications, particularly HDLC-based protocols, meet density requirements even across clear channel… |
1.3.6.1.4.1.466.4.4.6 | ty3250CfgDteIntfType | 1 | 1 | ty3250CfgDteIntftype |