This selection controls how the unit internally latches
the transmit data from the DTE. Normal will sample
data with the rising edge of the selected TX Clock,
Invert will sample data with the falling edge of the
selected TX Clock. The TX Clock is selected using
CfgDteTiming. This clock invertion is most useful when
loop-2 timing is used - particularly at higher rates
and with long cable runs. Only in rare circumstances
will clock-invert be used with loop-1 timing. If the
DTE Interface TX statistics are indicating excessive
crc errors or aborts then changing this setting may have
some benefit.
(1) normal
(2) invert
Parsed from file SFRAP.MIB.txt
Company: None
Module: SFRAP-MIB
This selection controls how the unit internally latches
the transmit data from the DTE. Normal will sample
data with the rising edge of the selected TX Clock,
Invert will sample data with the falling edge of the
selected TX Clock. The TX Clock is selected using
CfgDteTiming. This clock invertion is most useful when
loop-2 timing is used - particularly at higher rates
and with long cable runs. Only in rare circumstances
will clock-invert be used with loop-1 timing. If the
DTE Interface TX statistics are indicating excessive
crc errors or aborts then changing this setting may have
some benefit.
(1) normal
(2) invert
Parsed from file SFRAP-MIB.mib
Module: SFRAP-MIB
Vendor: Sync Research, Inc.
Module: SFRAP-MIB
[Automatically extracted from oidview.com]
sfrapCfgDteTxClockMode OBJECT-TYPE SYNTAX INTEGER { clock-normal (1), clock-invert (2) } ACCESS read-write STATUS mandatory DESCRIPTION "This selection controls how the unit internally latches the transmit data from the DTE. Normal will sample data with the rising edge of the selected TX Clock, Invert will sample data with the falling edge of the selected TX Clock. The TX Clock is selected using CfgDteTiming. This clock invertion is most useful when loop-2 timing is used - particularly at higher rates and with long cable runs. Only in rare circumstances will clock-invert be used with loop-1 timing. If the DTE Interface TX statistics are indicating excessive crc errors or aborts then changing this setting may have some benefit. (1) normal (2) invert" ::= { sfrapCfgDteEntry 3 }
sfrapCfgDteTxClockMode OBJECT-TYPE SYNTAX INTEGER { clock-normal (1), clock-invert (2) } ACCESS read-write STATUS mandatory DESCRIPTION "This selection controls how the unit internally latches the transmit data from the DTE. Normal will sample data with the rising edge of the selected TX Clock, Invert will sample data with the falling edge of the selected TX Clock. The TX Clock is selected using CfgDteTiming. This clock invertion is most useful when loop-2 timing is used - particularly at higher rates and with long cable runs. Only in rare circumstances will clock-invert be used with loop-1 timing. If the DTE Interface TX statistics are indicating excessive crc errors or aborts then changing this setting may have some benefit. (1) normal (2) invert" ::= { sfrapCfgDteEntry 3 }
| OID | Name | Sub children | Sub Nodes Total | Description |
|---|---|---|---|---|
| 1.3.6.1.4.1.485.7.2.4.1.1 | sfrapCfgDteIntfType | 0 | 0 | sfrapCfgDteIntftype |
| 1.3.6.1.4.1.485.7.2.4.1.21 | sfrapCfgDteRxClockMode | 0 | 0 | Clock-normal samples data with the rising edge of the selected rx clock, clock-invert samples data with the falling edge of the s… |
| 1.3.6.1.4.1.485.7.2.4.1.22 | sfrapCfgDteRtsC | 0 | 0 | Controls the reporting of the status of the To-DTE port's Request to Send (RTS) and Control (C) control signals, specifically the… |
| 1.3.6.1.4.1.485.7.2.4.1.99 | sfrapCfgDteIndex | 0 | 0 | Selects which DTE port. |