This attribute defines the intended gender of the HSSI port. The
actual gender of the port is determined by the hardware setup.
In dte mode, the ta line signal is driven as specified by the attribute
readyLineState when the HSSI port passes its diagnostics. The ta
line signal is then driven as specified by the attribute
dataTransferLineState when the application is ready to transfer
data. On the other hand, the input line signal ca is compared against
those specified in the attributes readyLineState and
dataTransferLineState. The application will be notified when the
specified input line states are observed.
In dce mode, the Hssi component behaves similarly as when it is in
dte mode. However, it will be driving the dce line signal (ca) and
monitoring the dte line signal (ta) as specified by the attributes
readyLineState and dataTransferLineState.
Parsed from file nortelPP-logicalProcessorV1_BG00S4C.mib.txt
Company: None
Module: Nortel-Magellan-Passport-LogicalProcessorMIB
This attribute defines the intended gender of the HSSI port. The
actual gender of the port is determined by the hardware setup.
In dte mode, the ta line signal is driven as specified by the attribute
readyLineState when the HSSI port passes its diagnostics. The ta
line signal is then driven as specified by the attribute
dataTransferLineState when the application is ready to transfer
data. On the other hand, the input line signal ca is compared against
those specified in the attributes readyLineState and
dataTransferLineState. The application will be notified when the
specified input line states are observed.
In dce mode, the Hssi component behaves similarly as when it is in
dte mode. However, it will be driving the dce line signal (ca) and
monitoring the dte line signal (ta) as specified by the attributes
readyLineState and dataTransferLineState.
Parsed from file Nortel-Magellan-Passport-LogicalProcessorMIB.mib
Module: Nortel-Magellan-Passport-LogicalProcessorMIB
Vendor: Northern Telecom, Ltd.
Module: Nortel-Magellan-Passport-LogicalProcessorMIB
[Automatically extracted from oidview.com]
lpHssiLinkMode OBJECT-TYPE SYNTAX INTEGER { dte(0), dce(128) } ACCESS read-write STATUS mandatory DESCRIPTION "This attribute defines the intended gender of the HSSI port. The actual gender of the port is determined by the hardware setup. In dte mode, the ta line signal is driven as specified by the attribute readyLineState when the HSSI port passes its diagnostics. The ta line signal is then driven as specified by the attribute dataTransferLineState when the application is ready to transfer data. On the other hand, the input line signal ca is compared against those specified in the attributes readyLineState and dataTransferLineState. The application will be notified when the specified input line states are observed. In dce mode, the Hssi component behaves similarly as when it is in dte mode. However, it will be driving the dce line signal (ca) and monitoring the dte line signal (ta) as specified by the attributes readyLineState and dataTransferLineState." DEFVAL { dce } ::= { lpHssiProvEntry 1 }
lpHssiLinkMode OBJECT-TYPE SYNTAX INTEGER { dte(0), dce(128) } ACCESS read-write STATUS mandatory DESCRIPTION "This attribute defines the intended gender of the HSSI port. The actual gender of the port is determined by the hardware setup. In dte mode, the ta line signal is driven as specified by the attribute readyLineState when the HSSI port passes its diagnostics. The ta line signal is then driven as specified by the attribute dataTransferLineState when the application is ready to transfer data. On the other hand, the input line signal ca is compared against those specified in the attributes readyLineState and dataTransferLineState. The application will be notified when the specified input line states are observed. In dce mode, the Hssi component behaves similarly as when it is in dte mode. However, it will be driving the dce line signal (ca) and monitoring the dte line signal (ta) as specified by the attributes readyLineState and dataTransferLineState." DEFVAL { dce } ::= { lpHssiProvEntry 1 }
| OID | Name | Sub children | Sub Nodes Total | Description |
|---|---|---|---|---|
| 1.3.6.1.4.1.562.2.4.1.12.17.10.1.2 | lpHssiReadyLineState | 0 | 0 | This attribute specifies the line signal originating from the HSSI interface that will always be turned on, provided the HSSI in… |
| 1.3.6.1.4.1.562.2.4.1.12.17.10.1.3 | lpHssiDataTransferLineState | 0 | 0 | This attribute specifies the line signals required to indicate that the external equipment is in a good state (that is, data tra… |
| 1.3.6.1.4.1.562.2.4.1.12.17.10.1.5 | lpHssiLineSpeed | 0 | 0 | This attribute defines the speed of the line for source clocking. This attribute is ignored if the interface is not providing a … |
| 1.3.6.1.4.1.562.2.4.1.12.17.10.1.7 | lpHssiApplicationFramerName | 0 | 0 | This attribute contains the component name of a Framer which is associated with the Hssi component. |