An entry in the ATM electrical interface (AEI)
port defects table. There will
be one entry for each defect (i.e error/warning)
configured. Notice that according to the defect
number, default value of each parameter of the
instance may be different between two instances.
Parsed from file ADN-ENV-MIB.mib
Module: ADN-ENV-MIB
Vendor: Alcatel-Lucent (previously was 'Alcatel Data Network')
Module: ADN-ENV-MIB
[Automatically extracted from oidview.com]
adnAeiPortDefEntry OBJECT-TYPE SYNTAX AdnAeiPortDefEntry ACCESS not-accessible STATUS mandatory DESCRIPTION "An entry in the ATM electrical interface (AEI) port defects table. There will be one entry for each defect (i.e error/warning) configured. Notice that according to the defect number, default value of each parameter of the instance may be different between two instances." INDEX { adnAeiPortDefBoardType, adnAeiPortDefNumber } ::= { adnAeiPortDefTable 1 }
| OID | Name | Sub children | Sub Nodes Total | Description |
|---|---|---|---|---|
| 1.3.6.1.4.1.637.3.1.8.5.5.21.1.1 | adnAeiPortDefBoardType | 0 | 0 | This is the ATM board type. |
| 1.3.6.1.4.1.637.3.1.8.5.5.21.1.2 | adnAeiPortDefNumber | 0 | 0 | This indicates the defect number. The description of each defect is given via the adnAtmPortErASEStatus for ASE board, the adnAtm… |
| 1.3.6.1.4.1.637.3.1.8.5.5.21.1.3 | adnAeiPortDefEventClass | 0 | 0 | This indicates the event class from hardware side: event: single fault signalled by the hardware or another software module to th… |
| 1.3.6.1.4.1.637.3.1.8.5.5.21.1.4 | adnAeiPortDefDirection | 0 | 0 | This indicates the direction of the defect when it occurs. |
| 1.3.6.1.4.1.637.3.1.8.5.5.21.1.5 | adnAeiPortDefBegThreshold | 0 | 0 | This indicates the number of times an error is detected within a time period (defined by adnAeiPortDefBegTimer) before an event (… |
| 1.3.6.1.4.1.637.3.1.8.5.5.21.1.6 | adnAeiPortDefEndThreshold | 0 | 0 | This indicates the maximum number of times a condition may be detected within a time period (defined by adnAeiPortDefEndTimer) be… |
| 1.3.6.1.4.1.637.3.1.8.5.5.21.1.7 | adnAeiPortDefBegTimer | 0 | 0 | This indicates the beginning timer in milliseconds during which the first appearance of an error is controlled. |
| 1.3.6.1.4.1.637.3.1.8.5.5.21.1.8 | adnAeiPortDefEndTimer | 0 | 0 | This indicates the end timer in milliseconds during which the disappearance of an error is controlled. |
| 1.3.6.1.4.1.637.3.1.8.5.5.21.1.9 | adnAeiPortDefSignalling | 0 | 0 | This indicates the defect signalling in addition to the report towards the control unit (CU). It is coded as a bit map. The variou… |
| 1.3.6.1.4.1.637.3.1.8.5.5.21.1.10 | adnAeiPortDefErrOrWng | 0 | 0 | This indicates the defect type (i.e error or warning); an error is a critical defect which modifies the operational state of the … |
| 1.3.6.1.4.1.637.3.1.8.5.5.21.1.11 | adnAeiPortDefReportEnable | 0 | 0 | This indicates the report control of the defect towards the control unit (CU). |