Number of L3 packets processed with a Level 3 checksum error.
Availability may depend on HW type, such as ASIC HW.
Number of L3 packets processed with a Level 3 checksum error.
Availability may depend on HW type, such as ASIC HW.
Parsed from file LS2020-R2-MIB.my.txt
Company: None
Module: LIGHTSTREAM-MIB
Number of L3 packets processed with a Level 3 checksum error.
Availability may depend on HW type, such as ASIC HW.
Parsed from file LIGHTSTREAM-MIB.mib
Module: LIGHTSTREAM-MIB
edgePortRcvL3XsumErrs OBJECT-TYPE SYNTAX Counter ACCESS read-only STATUS mandatory DESCRIPTION "Number of L3 packets processed with a Level 3 checksum error. Availability may depend on HW type, such as ASIC HW." ::= { lsEdgePortStatEntry 13 }
Vendor: Cisco Systems
Module: LIGHTSTREAM-MIB (LS2020-R2-MIB.my)
Type: TABULAR
Access: read-only
Syntax: Counter
Automatically extracted from www.mibdepot.com
edgePortRcvL3XsumErrs OBJECT-TYPE SYNTAX Counter ACCESS read-only STATUS mandatory DESCRIPTION "Number of L3 packets processed with a Level 3 checksum error. Availability may depend on HW type, such as ASIC HW." ::= { lsEdgePortStatEntry 13 }
edgePortRcvL3XsumErrs OBJECT-TYPE SYNTAX Counter ACCESS read-only STATUS mandatory DESCRIPTION "Number of L3 packets processed with a Level 3 checksum error. Availability may depend on HW type, such as ASIC HW." ::= { lsEdgePortStatEntry 13 }
OID | Name | Sub children | Sub Nodes Total | Description |
---|---|---|---|---|
1.3.6.1.4.1.711.2.1.11.1.1.2.1.1 | edgePortStatIndex | 0 | 0 | This is the ifIndex value of the corresponding ifEntry. See comments above. |
1.3.6.1.4.1.711.2.1.11.1.1.2.1.2 | edgePortRcvOctets | 0 | 0 | Number of octets received regardless of error status |
1.3.6.1.4.1.711.2.1.11.1.1.2.1.3 | edgePortXmtOctets | 0 | 0 | Number of octets transmitted regardless of error status |
1.3.6.1.4.1.711.2.1.11.1.1.2.1.4 | edgePortFsuCksmErrMsgs | 0 | 0 | The number of messages with AAL5 checksum errors detected by FSU. May not be provided on a per-port basis in all HW. |
1.3.6.1.4.1.711.2.1.11.1.1.2.1.5 | edgePortCksmErrLastVci | 0 | 0 | The last Vci index associated with a AAL5 checksum error. May not be provided on a per-port basis in all HW. |
1.3.6.1.4.1.711.2.1.11.1.1.2.1.6 | edgePortDownXmtFrames | 0 | 0 | The number of messages received by the TSU for which the the VCI was not configured. |
1.3.6.1.4.1.711.2.1.11.1.1.2.1.7 | edgePortRcvUcastPkts | 0 | 0 | Number of Unicast packets received. Availability may depend on HW type, such as ASIC HW. |
1.3.6.1.4.1.711.2.1.11.1.1.2.1.8 | edgePortRcvNUcastPkts | 0 | 0 | Number of Non-Unicast packets received. Availability may depend on HW type, such as ASIC HW. |
1.3.6.1.4.1.711.2.1.11.1.1.2.1.9 | edgePortXmtUcastPkts | 0 | 0 | Number of Unicast packets transmitted. Availability may depend on HW type, such as ASIC HW. |
1.3.6.1.4.1.711.2.1.11.1.1.2.1.10 | edgePortXmtNUcastPkts | 0 | 0 | Number of Non-Unicast packets transmitted. Availability may depend on HW type, such as ASIC HW. |
1.3.6.1.4.1.711.2.1.11.1.1.2.1.11 | edgePortRcvSmplPktSize | 0 | 0 | Number of octets for the last sampled from-port packet, including overhead octets. Used as a substitute for the frame size hist… |
1.3.6.1.4.1.711.2.1.11.1.1.2.1.12 | edgePortXmtSmplPktSize | 0 | 0 | Number of octets for the last sampled to-port packet, including overhead octets. Used as a substitute for the frame size histog… |
1.3.6.1.4.1.711.2.1.11.1.1.2.1.14 | edgePortRcvL3XsumErrLastVci | 0 | 0 | Last 15-bit VCI index associated with a Level 3 checksum error. Availability may depend on HW type, such as ASIC HW. |
1.3.6.1.4.1.711.2.1.11.1.1.2.1.15 | edgePortRcvCRCErrors | 0 | 0 | The number of messages received by the port with CRC errors. |
1.3.6.1.4.1.711.2.1.11.1.1.2.1.16 | edgePortRcvAborts | 0 | 0 | The number of aborts detected by the HW. |
1.3.6.1.4.1.711.2.1.11.1.1.2.1.17 | edgePortXmtUnderflows | 0 | 0 | The number of underflow events detected by I/O hardware. |
1.3.6.1.4.1.711.2.1.11.1.1.2.1.18 | edgePortRcvShortFrames | 0 | 0 | The number of short incoming frames detected by L2 |