Each entry represents a processor and is updated
at end of interval specified by the
cimrMsuRateSampleInterval object.
Parsed from file CISCO-ITP-MSU-RATES-MIB.mib
Module: CISCO-ITP-MSU-RATES-MIB
Each entry represents a processor and is updated
at end of interval specified by the
cimrMsuRateSampleInterval object.
Each entry represents a processor and is updated
at end of interval specified by the
cimrMsuRateSampleInterval object.
Parsed from file CISCO-ITP-MSU-RATES-MIB.my.txt
Company: None
Module: CISCO-ITP-MSU-RATES-MIB
Each entry represents a processor and is updated
at end of interval specified by the
cimrMsuRateSampleInterval object.
cimrMsuDistEntry OBJECT-TYPE SYNTAX CimrMsuDistEntry MAX-ACCESS not-accessible STATUS current DESCRIPTION "Each entry represents a processor and is updated at end of interval specified by the cimrMsuRateSampleInterval object." INDEX { cimrMsuProcIndex, cimrMsuTrafficDirection } ::= { cimrMsuDistTable 1 }
cimrMsuDistEntry OBJECT-TYPE SYNTAX CimrMsuDistEntry ACCESS not-accessible STATUS mandatory DESCRIPTION "Each entry represents a processor and is updated at end of interval specified by the cimrMsuRateSampleInterval object." INDEX { cimrMsuProcIndex, cimrMsuTrafficDirection } ::= { cimrMsuDistTable 1 }
Vendor: Cisco
Module: CISCO-ITP-MSU-RATES-MIB
[Automatically extracted from oidview.com]
cimrMsuDistEntry OBJECT-TYPE SYNTAX CimrMsuDistEntry MAX-ACCESS not-accessible STATUS current DESCRIPTION "Each entry represents a processor and is updated at end of interval specified by the cimrMsuRateSampleInterval object." INDEX { cimrMsuProcIndex, cimrMsuTrafficDirection } ::= { cimrMsuDistTable 1 }
cimrMsuDistEntry OBJECT-TYPE SYNTAX CimrMsuDistEntry MAX-ACCESS not-accessible STATUS current DESCRIPTION "Each entry represents a processor and is updated at end of interval specified by the cimrMsuRateSampleInterval object." INDEX { cimrMsuProcIndex, cimrMsuTrafficDirection } ::= { cimrMsuDistTable 1 }
OID | Name | Sub children | Sub Nodes Total | Description |
---|---|---|---|---|
1.3.6.1.4.1.9.9.529.1.2.3.1.1 | cimrMsuDist000to009Seconds | 0 | 0 | The total number of seconds during which the MSU rate for this processor was from 0 to 9 percent of the current overloaded-thresh… |
1.3.6.1.4.1.9.9.529.1.2.3.1.2 | cimrMsuDist010to019Seconds | 0 | 0 | The total number of seconds during which the MSU rate for this processor was from 10 to 19 percent of the current overloaded-thre… |
1.3.6.1.4.1.9.9.529.1.2.3.1.3 | cimrMsuDist020to029Seconds | 0 | 0 | The total number of seconds during which the MSU rate for this processor was from 20 to 29 percent of the current overloaded-thre… |
1.3.6.1.4.1.9.9.529.1.2.3.1.4 | cimrMsuDist030to039Seconds | 0 | 0 | The total number of seconds during which the MSU rate for this processor was from 30 to 39 percent of the current overloaded-thre… |
1.3.6.1.4.1.9.9.529.1.2.3.1.5 | cimrMsuDist040to049Seconds | 0 | 0 | The total number of seconds during which the MSU rate for this processor was from 40 to 49 percent of the current overloaded-thre… |
1.3.6.1.4.1.9.9.529.1.2.3.1.6 | cimrMsuDist050to059Seconds | 0 | 0 | The total number of seconds during which the MSU rate for this processor was from 50 to 59 percent of the current overloaded-thre… |
1.3.6.1.4.1.9.9.529.1.2.3.1.7 | cimrMsuDist060to069Seconds | 0 | 0 | The total number of seconds during which the MSU rate for this processor was from 60 to 69 percent of the current overloaded-thre… |
1.3.6.1.4.1.9.9.529.1.2.3.1.8 | cimrMsuDist070to079Seconds | 0 | 0 | The total number of seconds during which the MSU rate for this processor was from 70 to 79 percent of the current overloaded-thre… |
1.3.6.1.4.1.9.9.529.1.2.3.1.9 | cimrMsuDist080to089Seconds | 0 | 0 | The total number of seconds during which the MSU rate for this processor was from 80 to 89 percent of the current overloaded-thre… |
1.3.6.1.4.1.9.9.529.1.2.3.1.10 | cimrMsuDist090orAbove | 0 | 0 | The total number of seconds during which the MSU rate for this processor was above 90 percent of the current overloaded-threshold… |