OID reference

issPortCpuControlledLearning

1.3.6.1.4.1.2076.81.2.2.1.11

Description

Enables or disables the CPU controlled learning on a port. The default behavior is hardware learning. By enabling this object software learning on that particular port is enabled. When CPU controlled learning is enabled, for the first time, packet will be copied to CPU and source MAC address learning will not happen i…

Full description and source information

Identification

Identifier and names

Parent
1.3.6.1.4.1.2076.81.2.2.1 (issPortCtrlEntry)
Node code
11
Node name
issPortCpuControlledLearning
Category
SNMP management object
Numeric OID
1.3.6.1.4.1.2076.81.2.2.1.11
URN notation
urn:oid:1.3.6.1.4.1.2076.81.2.2.1.11
ASN.1, OID-IRI and named path variants
ASN.1 notation

{1 3 6 1 4 1 2076 81 2 2 1 11}

  • {iso(1) identified-organization(3) dod(6) internet(1) private(4) enterprise(1) 2076 iss(81) issConfigControl(2) issPortCtrlTable(2) issPortCtrlEntry(1) issPortCpuControlledLearning(11)}
  • {iso(1) identified-organization(3) dod(6) internet(1) private(4) enterprises(1) 2076 iss(81) issConfigControl(2) issPortCtrlTable(2) issPortCtrlEntry(1) issPortCpuControlledLearning(11)}
  • {iso(1) identified-organization(3) dod(6) internet(1) private(4) ldap-enterprise(1) 2076 iss(81) issConfigControl(2) issPortCtrlTable(2) issPortCtrlEntry(1) issPortCpuControlledLearning(11)}
  • {iso(1) identified-organization(3) dod(6) internet(1) private(4) vendor-objects(1) 2076 iss(81) issConfigControl(2) issPortCtrlTable(2) issPortCtrlEntry(1) issPortCpuControlledLearning(11)}
  • {iso(1) org(3) dod(6) internet(1) private(4) enterprise(1) 2076 iss(81) issConfigControl(2) issPortCtrlTable(2) issPortCtrlEntry(1) issPortCpuControlledLearning(11)}
  • {iso(1) org(3) dod(6) internet(1) private(4) enterprises(1) 2076 iss(81) issConfigControl(2) issPortCtrlTable(2) issPortCtrlEntry(1) issPortCpuControlledLearning(11)}
  • {iso(1) org(3) dod(6) internet(1) private(4) ldap-enterprise(1) 2076 iss(81) issConfigControl(2) issPortCtrlTable(2) issPortCtrlEntry(1) issPortCpuControlledLearning(11)}
  • {iso(1) org(3) dod(6) internet(1) private(4) vendor-objects(1) 2076 iss(81) issConfigControl(2) issPortCtrlTable(2) issPortCtrlEntry(1) issPortCpuControlledLearning(11)}
  • {iso(1) iso-identified-organization(3) dod(6) internet(1) private(4) enterprise(1) 2076 iss(81) issConfigControl(2) issPortCtrlTable(2) issPortCtrlEntry(1) issPortCpuControlledLearning(11)}
  • {iso(1) iso-identified-organization(3) dod(6) internet(1) private(4) enterprises(1) 2076 iss(81) issConfigControl(2) issPortCtrlTable(2) issPortCtrlEntry(1) issPortCpuControlledLearning(11)}
  • {iso(1) iso-identified-organization(3) dod(6) internet(1) private(4) ldap-enterprise(1) 2076 iss(81) issConfigControl(2) issPortCtrlTable(2) issPortCtrlEntry(1) issPortCpuControlledLearning(11)}
  • {iso(1) iso-identified-organization(3) dod(6) internet(1) private(4) vendor-objects(1) 2076 iss(81) issConfigControl(2) issPortCtrlTable(2) issPortCtrlEntry(1) issPortCpuControlledLearning(11)}
  • {iso(1) iso-organization(3) dod(6) internet(1) private(4) enterprise(1) 2076 iss(81) issConfigControl(2) issPortCtrlTable(2) issPortCtrlEntry(1) issPortCpuControlledLearning(11)}
  • {iso(1) iso-organization(3) dod(6) internet(1) private(4) enterprises(1) 2076 iss(81) issConfigControl(2) issPortCtrlTable(2) issPortCtrlEntry(1) issPortCpuControlledLearning(11)}
  • {iso(1) iso-organization(3) dod(6) internet(1) private(4) ldap-enterprise(1) 2076 iss(81) issConfigControl(2) issPortCtrlTable(2) issPortCtrlEntry(1) issPortCpuControlledLearning(11)}
  • {iso(1) iso-organization(3) dod(6) internet(1) private(4) vendor-objects(1) 2076 iss(81) issConfigControl(2) issPortCtrlTable(2) issPortCtrlEntry(1) issPortCpuControlledLearning(11)}
OID-IRI notation
  • /1/3/6/1/4/1/2076/81/2/2/1/11
  • /ISO/Identified-Organization/6/1/4/1/2076/81/2/2/1/11
  • /ISO/3/6/1/4/1/2076/81/2/2/1/11
Named path variants
  • /iso/identified-organization/dod/internet/private/enterprise/2076/iss/issConfigControl/issPortCtrlTable/issPortCtrlEntry/issPortCpuControlledLearning
  • /iso/identified-organization/dod/internet/private/enterprises/2076/iss/issConfigControl/issPortCtrlTable/issPortCtrlEntry/issPortCpuControlledLearning
  • /iso/identified-organization/dod/internet/private/ldap-enterprise/2076/iss/issConfigControl/issPortCtrlTable/issPortCtrlEntry/issPortCpuControlledLearning
  • /iso/identified-organization/dod/internet/private/vendor-objects/2076/iss/issConfigControl/issPortCtrlTable/issPortCtrlEntry/issPortCpuControlledLearning
  • /iso/org/dod/internet/private/enterprise/2076/iss/issConfigControl/issPortCtrlTable/issPortCtrlEntry/issPortCpuControlledLearning
  • /iso/org/dod/internet/private/enterprises/2076/iss/issConfigControl/issPortCtrlTable/issPortCtrlEntry/issPortCpuControlledLearning
  • /iso/org/dod/internet/private/ldap-enterprise/2076/iss/issConfigControl/issPortCtrlTable/issPortCtrlEntry/issPortCpuControlledLearning
  • /iso/org/dod/internet/private/vendor-objects/2076/iss/issConfigControl/issPortCtrlTable/issPortCtrlEntry/issPortCpuControlledLearning
  • /iso/iso-identified-organization/dod/internet/private/enterprise/2076/iss/issConfigControl/issPortCtrlTable/issPortCtrlEntry/issPortCpuControlledLearning
  • /iso/iso-identified-organization/dod/internet/private/enterprises/2076/iss/issConfigControl/issPortCtrlTable/issPortCtrlEntry/issPortCpuControlledLearning
  • /iso/iso-identified-organization/dod/internet/private/ldap-enterprise/2076/iss/issConfigControl/issPortCtrlTable/issPortCtrlEntry/issPortCpuControlledLearning
  • /iso/iso-identified-organization/dod/internet/private/vendor-objects/2076/iss/issConfigControl/issPortCtrlTable/issPortCtrlEntry/issPortCpuControlledLearning
  • /iso/iso-organization/dod/internet/private/enterprise/2076/iss/issConfigControl/issPortCtrlTable/issPortCtrlEntry/issPortCpuControlledLearning
  • /iso/iso-organization/dod/internet/private/enterprises/2076/iss/issConfigControl/issPortCtrlTable/issPortCtrlEntry/issPortCpuControlledLearning
  • /iso/iso-organization/dod/internet/private/ldap-enterprise/2076/iss/issConfigControl/issPortCtrlTable/issPortCtrlEntry/issPortCpuControlledLearning
  • /iso/iso-organization/dod/internet/private/vendor-objects/2076/iss/issConfigControl/issPortCtrlTable/issPortCtrlEntry/issPortCpuControlledLearning

SNMP properties

Value type
INTEGER
Maximum access defined by MIB
read-write
Status in MIB
current
Default value
disabled

Enumerated values

ValueName
1disabled
2enabled

Using this OID with SNMP

At least one MIB declaration places this object in a table row. A value belongs to a row instance; its suffix depends on the row's INDEX or AUGMENTS definition.

In ARICENT-ISS-MIB, the row index issPortCtrlIndex is declared as Integer32. A non-negative index value is encoded as one numeric subidentifier. An instance has the form .1.3.6.1.4.1.2076.81.2.2.1.11.<issPortCtrlIndex>. Use an index value actually present on the device and permitted by its MIB. Other definitions can differ.

Published row index: issPortCtrlIndex.

snmpwalk [connection options] DEVICE .1.3.6.1.4.1.2076.81.2.2.1.11

Replace the placeholders with your connection and authentication options. Available permissions and device support can differ from the MIB.

Properties come from available MIB definitions. Actual device support and access can differ. See source records below for original files and qualifications.

Available source records contain 2 distinct definitions; some records may not include a definition.

Show 2 published definitions

issPortCpuControlledLearning · current

issPortCpuControlledLearning OBJECT-TYPE
   SYNTAX       INTEGER {
                   disabled  (1),
                   enabled   (2)
                }
   MAX-ACCESS  read-write
   STATUS      current
   DESCRIPTION 
      "Enables or disables the CPU controlled learning on a port. 
       The default behavior is hardware learning. By enabling this object 
       software learning on that particular port is enabled.

       When CPU controlled learning is enabled, for the first time, packet 
       will be copied to CPU and source MAC address learning will not happen 
       in the hardware. When packet is received at PNAC - if the source MAC 
       address is authorized, the packet will be allowed to go through further 
       processing. Else, the packet will be dropped.  When packets from 
       authorized MAC address are received at VLAN, MAC learning will happen 
       at VLAN and the same entry will be programmed in the hardware. Once the 
       MAC address is learnt, further forwarding will happen at driver itself.    

       The Mac address entries which are added through software learning are
       checked in periodical intervals for the HIT entry. If there is no
       traffic for that entry, the HIT flag won't be set. The entry will be 
       removed from the hardware if the hit flag is not set.
       Note: When software learning is enabled, rate limiting to the port
       needs to be configured"

   DEFVAL  { disabled }
   ::= { issPortCtrlEntry 11 }

issPortCpuControlledLearning · current

issPortCpuControlledLearning OBJECT-TYPE
   SYNTAX       INTEGER {
                   disabled  (1),
                   enabled   (2)
                }
   MAX-ACCESS  read-write
   STATUS      current
   DESCRIPTION
      "Enables or disables the CPU controlled learning on a port.
       The default behavior is hardware learning. By enabling this object
       software learning on that particular port is enabled.

       When CPU controlled learning is enabled, for the first time, packet
       will be copied to CPU and source MAC address learning will not happen
       in the hardware. When packet is received at PNAC - if the source MAC
       address is authorized, the packet will be allowed to go through further
       processing. Else, the packet will be dropped.  When packets from
       authorized MAC address are received at VLAN, MAC learning will happen
       at VLAN and the same entry will be programmed in the hardware. Once the
       MAC address is learnt, further forwarding will happen at driver itself.

       The Mac address entries which are added through software learning are
       checked in periodical intervals for the HIT entry. If there is no
       traffic for that entry, the HIT flag won't be set. The entry will be
       removed from the hardware if the hit flag is not set.
       Note: When software learning is enabled, rate limiting to the port
       needs to be configured"

   DEFVAL  { disabled }
   ::= { issPortCtrlEntry 11 }

Meaning

Descriptions

1 unique

Identical descriptions are grouped. Different wording and device-specific notes are retained.

Enables or disables the CPU controlled learning on a port. The default behavior is hardware learning. By enabling this object software learning on that particular port is enabled. When CPU controlled learning is enabled, for the first time, packet will be copied to CPU and source MAC address learning will not happen in the hardware. When packet is received at PNAC - if the source MAC address is authorized, the packet will be allowed to go through further processing. Else, the packet will be dropped. When packets from authorized MAC address are received at VLAN, MAC learning will happen at VLAN and the same entry will be programmed in the hardware. Once the MAC address is learnt, further forwarding will happen at driver itself. The Mac address entries which are added through software learning are checked in periodical intervals for the HIT entry. If there is no traffic for that entry, the HIT flag won't be set. The entry will be removed from the hardware if the hit flag is not set. Note: When software learning is enabled, rate limiting to the port needs to be configured

Sources for this description

Multiple manufacturers; see the original MIB MIB copies (LibreNMS/Observium Community)

See 1 matching source record

Evidence

Source records

1 records

Matching descriptions are grouped; open a group to compare definitions and supporting files.

Records for description 1Multiple manufacturers; see the original MIB MIB copies (LibreNMS/Observium Community)1 record · 3 sources

Description 1

issPortCpuControlledLearning · currentMultiple manufacturers; see the original MIB MIB copies (LibreNMS/Observium Community)3 sources

Status in source: current.

Names: issPortCpuControlledLearning

Technical details
{
  "smi_kind": "OBJECT-TYPE",
  "definition": [
    "issPortCpuControlledLearning",
    "OBJECT-TYPE",
    "SYNTAX",
    "INTEGER",
    "{",
    "disabled",
    "(",
    "1",
    ")",
    ",",
    "enabled",
    "(",
    "2",
    ")",
    "}",
    "MAX-ACCESS",
    "read-write",
    "STATUS",
    "current",
    "DESCRIPTION",
    "\"Enables or disables the CPU controlled learning on a port. The default behavior is hardware learning. By enabling this object software learning on that particular port is enabled. When CPU controlled learning is enabled, for the first time, packet will be copied to CPU and source MAC address learning will not happen in the hardware. When packet is received at PNAC - if the source MAC address is authorized, the packet will be allowed to go through further processing. Else, the packet will be dropped. When packets from authorized MAC address are received at VLAN, MAC learning will happen at VLAN and the same entry will be programmed in the hardware. Once the MAC address is learnt, further forwarding will happen at driver itself. The Mac address entries which are added through software learning are checked in periodical intervals for the HIT entry. If there is no traffic for that entry, the HIT flag won't be set. The entry will be removed from the hardware if the hit flag is not set. Note: When software learning is enabled, rate limiting to the port needs to be configured\"",
    "DEFVAL",
    "{",
    "disabled",
    "}",
    "::=",
    "{",
    "issPortCtrlEntry",
    "11",
    "}"
  ],
  "syntax_tree": [
    [
      "SimpleSyntax",
      "INTEGER",
      [
        "enumSpec",
        [
          [
            "disabled",
            1
          ],
          [
            "enabled",
            2
          ]
        ]
      ]
    ],
    null,
    [
      "MaxAccessPart",
      "read-write"
    ],
    [
      "Status",
      "current"
    ],
    [
      "DESCRIPTION",
      "Enables or disables the CPU controlled learning on a port. The default behavior is hardware learning. By enabling this object software learning on that particular port is enabled. When CPU controlled learning is enabled, for the first time, packet will be copied to CPU and source MAC address learning will not happen in the hardware. When packet is received at PNAC - if the source MAC address is authorized, the packet will be allowed to go through further processing. Else, the packet will be dropped. When packets from authorized MAC address are received at VLAN, MAC learning will happen at VLAN and the same entry will be programmed in the hardware. Once the MAC address is learnt, further forwarding will happen at driver itself. The Mac address entries which are added through software learning are checked in periodical intervals for the HIT entry. If there is no traffic for that entry, the HIT flag won't be set. The entry will be removed from the hardware if the hit flag is not set. Note: When software learning is enabled, rate limiting to the port needs to be configured"
    ],
    null,
    null,
    null,
    [
      "DEFVAL",
      "disabled"
    ]
  ]
}

Registration

Registration authorities

First Registration Authority (inferred from ancestor 1.3.6.1.4.1.2076)

Division Products

Siblings (25)

OIDNameDirect childrenDescendantsDescription
1.3.6.1.4.1.2076.81.2.2.1.1 issPortCtrlIndex00
1.3.6.1.4.1.2076.81.2.2.1.2 issPortCtrlMode00
1.3.6.1.4.1.2076.81.2.2.1.3 issPortCtrlDuplex00
1.3.6.1.4.1.2076.81.2.2.1.4 issPortCtrlSpeed00
1.3.6.1.4.1.2076.81.2.2.1.5 issPortCtrlFlowControl00
1.3.6.1.4.1.2076.81.2.2.1.6 issPortCtrlRenegotiate00
1.3.6.1.4.1.2076.81.2.2.1.7 issPortCtrlMaxMacAddr00
1.3.6.1.4.1.2076.81.2.2.1.8 issPortCtrlMaxMacAction00
1.3.6.1.4.1.2076.81.2.2.1.9 issPortHOLBlockPrevention00
1.3.6.1.4.1.2076.81.2.2.1.10 issPortAutoNegAdvtCapBits00
1.3.6.1.4.1.2076.81.2.2.1.12 issPortMdiOrMdixCap00
1.3.6.1.4.1.2076.81.2.2.1.13 issPortCtrlFlowControlMaxRate00
1.3.6.1.4.1.2076.81.2.2.1.14 issPortCtrlFlowControlMinRate00
1.3.6.1.4.1.2076.81.2.2.1.15 issPortCtrlPauseFloodProtect00
1.3.6.1.4.1.2076.81.2.2.1.16 issPortCtrlPauseFloodMode00
1.3.6.1.4.1.2076.81.2.2.1.17 issPortCtrlPauseFloodStatus00
1.3.6.1.4.1.2076.81.2.2.1.18 issPortCtrlPauseFloodReset00
1.3.6.1.4.1.2076.81.2.2.1.19 issPortCtrlPauseFloodStats00
1.3.6.1.4.1.2076.81.2.2.1.20 issPortCtrlPauseFloodStatsClear00
1.3.6.1.4.1.2076.81.2.2.1.21 issPortCtrlPauseFloodTraceOption00
1.3.6.1.4.1.2076.81.2.2.1.22 issPortCtrlSwitchModeType00
1.3.6.1.4.1.2076.81.2.2.1.23 issPortCtrlSwitchModeStatus00
1.3.6.1.4.1.2076.81.2.2.1.24 issPortCtrlInbandAutoNeg00
1.3.6.1.4.1.2076.81.2.2.1.25 issPortCtrlBypassInbandAutoNeg00
1.3.6.1.4.1.2076.81.2.2.1.26 issPortCtrlForceSpeed00