CPU Rate Limit table entry
Sources for this description
Multiple manufacturers; see the original MIB MIB copies (LibreNMS/Observium Community)
OID reference
1.3.6.1.4.1.29601.2.6.1.6.1.1
CPU Rate Limit table entry
Identification
{1 3 6 1 4 1 29601 2 6 1 6 1 1}
Properties come from available MIB definitions. Actual device support and access can differ. See source records below for original files and qualifications.
The displayed source records contain one distinct definition. Compare its source records.
fsQosHwCpuRateLimitEntry OBJECT-TYPE
SYNTAX FsQosHwCpuRateLimitEntry
MAX-ACCESS not-accessible
STATUS current
DESCRIPTION " CPU Rate Limit table entry"
INDEX {fsQosHwCpuQId }
::= { fsQosHwCpuRateLimitTable 1 }
Meaning
Identical descriptions are grouped. Different wording and device-specific notes are retained.
CPU Rate Limit table entry
Multiple manufacturers; see the original MIB MIB copies (LibreNMS/Observium Community)
Evidence
Matching descriptions are grouped; open a group to compare definitions and supporting files.
Status in source: current.
Names: fsQosHwCpuRateLimitEntry
{
"smi_kind": "OBJECT-TYPE",
"definition": [
"fsQosHwCpuRateLimitEntry",
"OBJECT-TYPE",
"SYNTAX",
"FsQosHwCpuRateLimitEntry",
"MAX-ACCESS",
"not-accessible",
"STATUS",
"current",
"DESCRIPTION",
"\" CPU Rate Limit table entry\"",
"INDEX",
"{",
"fsQosHwCpuQId",
"}",
"::=",
"{",
"fsQosHwCpuRateLimitTable",
"1",
"}"
],
"syntax_tree": [
[
"row",
"FsQosHwCpuRateLimitEntry"
],
null,
[
"MaxAccessPart",
"not-accessible"
],
[
"Status",
"current"
],
[
"DESCRIPTION",
"CPU Rate Limit table entry"
],
null,
null,
[
"INDEX",
[
[
0,
"fsQosHwCpuQId"
]
]
],
null
]
}Vendor MIB copy from the Observium Community archive.
Module: ARICENT-DIFFSERV-MIB
See published definition above
{'IF-MIB': ['ifIndex'], 'SNMPv2-TC': ['TEXTUAL-CONVENTION', 'RowStatus', 'DisplayString', 'TruthValue'], 'SNMPv2-SMI': ['Unsigned32', 'MODULE-IDENTITY', 'OBJECT-TYPE', 'enterprises', 'Integer32', 'Counter64']}Related source files and packages:
Vendor MIB copy from the Observium Community archive.
Module: ARICENT-QOS-MIB
{'IF-MIB': ['ifIndex'], 'SNMPv2-TC': ['TEXTUAL-CONVENTION', 'RowStatus', 'DisplayString', 'TruthValue'], 'SNMPv2-SMI': ['Unsigned32', 'MODULE-IDENTITY', 'OBJECT-TYPE', 'enterprises', 'Integer32', 'Counter64']}Registration
| OID | Name | Direct children | Descendants | Description |
|---|---|---|---|---|
| 1.3.6.1.4.1.29601.2.6.1.6.1.1.1 | fsQosHwCpuQId | 0 | 0 | |
| 1.3.6.1.4.1.29601.2.6.1.6.1.1.2 | fsQosHwCpuMinRate | 0 | 0 | |
| 1.3.6.1.4.1.29601.2.6.1.6.1.1.3 | fsQosHwCpuMaxRate | 0 | 0 | |
| 1.3.6.1.4.1.29601.2.6.1.6.1.1.4 | fsQosHwCpuRowStatus | 0 | 0 |