This trap indicates that a change in the trail trace
message was detected on the incoming signal.
Parsed from file fore-switch.mib.txt
Company: None
Module: Fore-Switch-MIB
This trap indicates that a change in the trail trace
message was detected on the incoming signal.
Parsed from file Fore-Switch-MIB.mib
Module: Fore-Switch-MIB
Vendor: Fore Systems, Inc.
Module: Fore-Switch-MIB
[Automatically extracted from oidview.com]
asxE3TrailChangeDetected NOTIFICATION-TYPE OBJECTS { hwPortName, hwPortBoard, hwPortModule, hwPortNumber, trapLogIndex } STATUS current DESCRIPTION "This trap indicates that a change in the trail trace message was detected on the incoming signal." ::= { atmSwitch 0 192 }
asxE3TrailChangeDetected NOTIFICATION-TYPE OBJECTS { hwPortName, hwPortBoard, hwPortModule, hwPortNumber, trapLogIndex } STATUS current DESCRIPTION "This trap indicates that a change in the trail trace message was detected on the incoming signal." ::= { atmSwitch 0 192 }
To many brothers! Only 100 nearest brothers are shown.
| OID | Name | Sub children | Sub Nodes Total | Description |
|---|---|---|---|---|
| ... | ||||
| 1.3.6.1.4.1.326.2.2.0.142 | asxSonetAtmLCDDetected | 0 | 0 | This trap indicates that the specified SONET port is experiencing Loss of Cell Deliniation (LCD). A LCD failure is declared when … |
| 1.3.6.1.4.1.326.2.2.0.143 | asxSonetAtmLCDCleared | 0 | 0 | This trap indicates that the LCD failure identified by trap asxSonetAtmLCDDetected has been cleared. A LCD failure is cleared whe… |
| 1.3.6.1.4.1.326.2.2.0.144 | asxSonetAtmLineBIPDetected | 0 | 0 | This trap indicates that the specified SONET port is experiencing Bit Interleaved Parity (BIP) errors. A Line BIP failure is decl… |
| 1.3.6.1.4.1.326.2.2.0.145 | asxSonetAtmLineBIPCleared | 0 | 0 | This trap indicates that the Line BIP failure identified by trap asxSonetAtmLineBIPDetected has been cleared. A Line BIP failure … |
| 1.3.6.1.4.1.326.2.2.0.160 | asxDS3IdleDetected | 0 | 0 | This trap indicates that an Idle Maintenance Signal (IDLE) is detected on the incoming signal. |
| 1.3.6.1.4.1.326.2.2.0.161 | asxDS3IdleCleared | 0 | 0 | This trap indicates that an Idle Maintenance Signal (IDLE) is cleared on the incoming signal. |
| 1.3.6.1.4.1.326.2.2.0.162 | asxDS3AtmLCDDetected | 0 | 0 | This trap indicates that the specified DS3 port is experiencing Loss of Cell Deliniation (LCD). A LCD failure is declared when th… |
| 1.3.6.1.4.1.326.2.2.0.163 | asxDS3AtmLCDCleared | 0 | 0 | This trap indicates that the LCD failure identified by trap asxDS3AtmLCDDetected has been cleared. A LCD failure is cleared when … |
| 1.3.6.1.4.1.326.2.2.0.164 | asxDS3PbitPerrDetected | 0 | 0 | This trap indicates that the specified DS3 port is experiencing P-bit Parity errors. A P-bit Parity Error failure is declared whe… |
| 1.3.6.1.4.1.326.2.2.0.165 | asxDS3PbitPerrCleared | 0 | 0 | This trap indicates that the P-bit Parity Error failure identified by trap asxDS3PbitPerrDetected has been cleared. A P-bit Parit… |
| 1.3.6.1.4.1.326.2.2.0.176 | asxDS1PRBSDetected | 0 | 0 | This trap indicates that PRBS pattern is detected on the incoming signal. |
| 1.3.6.1.4.1.326.2.2.0.177 | asxDS1PRBSCleared | 0 | 0 | This trap indicates that PRBS pattern is cleared on the incoming signal. |
| 1.3.6.1.4.1.326.2.2.0.178 | asxDS1AtmLCDDetected | 0 | 0 | This trap indicates that the specified DS1 port is experiencing Loss of Cell Deliniation (LCD). A LCD failure is declared when th… |
| 1.3.6.1.4.1.326.2.2.0.179 | asxDS1AtmLCDCleared | 0 | 0 | This trap indicates that the LCD failure identified by trap asxDS1AtmLCDDetected has been cleared. A LCD failure is cleared when … |
| 1.3.6.1.4.1.326.2.2.0.180 | asxDS1CRCErrDetected | 0 | 0 | This trap indicates that the specified DS1 port is experiencing excessive CRC-6 errors. A CRC-6 Error failure is declared when th… |
| 1.3.6.1.4.1.326.2.2.0.181 | asxDS1CRCErrCleared | 0 | 0 | This trap indicates that the excessive CRC-6 Error failure identified by trap asxDS1CRCErrDetected has been cleared. A CRC-6 Pari… |
| 1.3.6.1.4.1.326.2.2.0.208 | asxE1AtmLCDDetected | 0 | 0 | This trap indicates that the specified E1 port is experiencing Loss of Cell Deliniation (LCD). A LCD failure is declared when the… |
| 1.3.6.1.4.1.326.2.2.0.209 | asxE1AtmLCDCleared | 0 | 0 | This trap indicates that the LCD failure identified by trap asxE1AtmLCDDetected has been cleared. A LCD failure is cleared when t… |
| 1.3.6.1.4.1.326.2.2.0.224 | asxJ2RLOCDetected | 0 | 0 | This trap indicates that Receive Loss of Clock (RLOC) is detected on the incoming signal. |
| 1.3.6.1.4.1.326.2.2.0.225 | asxJ2RLOCCleared | 0 | 0 | This trap indicates that Receive Loss of Clock (RLOC) is cleared on the incoming signal. |
| 1.3.6.1.4.1.326.2.2.0.226 | asxJ2HBERDetected | 0 | 0 | This trap indicates that High Bit Error Rate (HBER) is detected on the incoming signal. |
| 1.3.6.1.4.1.326.2.2.0.227 | asxJ2HBERCleared | 0 | 0 | This trap indicates that High Bit Error Rate (HBER) is cleared on the incoming signal. |
| 1.3.6.1.4.1.326.2.2.0.228 | asxJ2PAISDetected | 0 | 0 | This trap indicates that Payload Alarm Indication Signal (PAIS) is detected on the incoming signal. |
| 1.3.6.1.4.1.326.2.2.0.229 | asxJ2PAISCleared | 0 | 0 | This trap indicates that Payload Alarm Indication SIgnal (PAIS) is cleared on the incoming signal. |
| 1.3.6.1.4.1.326.2.2.0.230 | asxJ2AtmLCDDetected | 0 | 0 | This trap indicates that the specified J2 port is experiencing Loss of Cell Deliniation (LCD). A LCD failure is declared when the… |
| 1.3.6.1.4.1.326.2.2.0.231 | asxJ2AtmLCDCleared | 0 | 0 | This trap indicates that the LCD failure identified by trap asxJ2AtmLCDDetected has been cleared. A LCD failure is cleared when t… |
| 1.3.6.1.4.1.326.2.2.0.232 | asxJ2TLOCDetected | 0 | 0 | This trap indicates that Transmit Loss of Clock (TLOC) is detected. |
| 1.3.6.1.4.1.326.2.2.0.233 | asxJ2TLOCCleared | 0 | 0 | This trap indicates that Transmit Loss of Clock (TLOC) is cleared. |
| ... | ||||