The class code register as defined in the PCI Local
Bus Specification in the following format:
Octet Register
1 Programming Interface
2 Sub-class code
3 Base class code
Parsed from file README1.TXT
Company: None
Module: CPQSTDEQ-MIB
The class code register as defined in the PCI Local
Bus Specification in the following format:
Octet Register
1 Programming Interface
2 Sub-class code
3 Base class code
Parsed from file CPQSTDEQ-MIB.mib
Module: CPQSTDEQ-MIB
cpqSePciFunctClassCode OBJECT-TYPE SYNTAX OCTET STRING (SIZE(0..3)) ACCESS read-only STATUS mandatory DESCRIPTION "The class code register as defined in the PCI Local Bus Specification in the following format: Octet Register 1 Programming Interface 2 Sub-class code 3 Base class code" ::= { cpqSePciFunctEntry 4 }
Vendor: Compaq
Module: CPQSTDEQ-MIB
[Automatically extracted from oidview.com]
cpqSePciFunctClassCode OBJECT-TYPE SYNTAX OCTET STRING (SIZE(0..3)) ACCESS read-only STATUS mandatory DESCRIPTION "The class code register as defined in the PCI Local Bus Specification in the following format: Octet Register 1 Programming Interface 2 Sub-class code 3 Base class code" ::= { cpqSePciFunctEntry 4 }
| OID | Name | Sub children | Sub Nodes Total | Description |
|---|---|---|---|---|
| 1.3.6.1.4.1.232.1.2.13.2.1.1 | cpqSePciFunctBusNumberIndex | 0 | 0 | The PCI bus number for this device function. |
| 1.3.6.1.4.1.232.1.2.13.2.1.2 | cpqSePciFunctDeviceNumberIndex | 0 | 0 | The device index for this function. |
| 1.3.6.1.4.1.232.1.2.13.2.1.3 | cpqSePciFunctIndex | 0 | 0 | The unique index that specifies this function. |
| 1.3.6.1.4.1.232.1.2.13.2.1.5 | cpqSePciFunctClassDescription | 0 | 0 | A text string which describes the PCI Base Class and Sub Class to which this device belongs. This field may empty if no descripti… |
| 1.3.6.1.4.1.232.1.2.13.2.1.6 | cpqSePciFunctDeviceID | 0 | 0 | This variable identifies this particular device. This identifier is allocated by the component manufacturer. |
| 1.3.6.1.4.1.232.1.2.13.2.1.7 | cpqSePciFunctVendorID | 0 | 0 | This variable identifies the component manufacturer. Valid identifiers are assigned by the PCI SIG. |
| 1.3.6.1.4.1.232.1.2.13.2.1.8 | cpqSePciFunctRevID | 0 | 0 | This variable is a vendor defined extension to the device ID and specifies a device specific revision identifier. |
| 1.3.6.1.4.1.232.1.2.13.2.1.9 | cpqSePciFunctIntLine | 0 | 0 | This variable specifies which input of the system interrupt controller(s) the device's interrupt pin is connected to. A value of … |
| 1.3.6.1.4.1.232.1.2.13.2.1.10 | cpqSePciFunctDevStatus | 0 | 0 | The status of the device described by this function. Some PCI devices, such as embedded devices, have the potential of being pres… |
| 1.3.6.1.4.1.232.1.2.13.2.1.11 | cpqSePciFunctHwLocation | 0 | 0 | A text description of the hardware location, on complex multi SBB hardware only, for the Peripheral Component Interconnect (PCI) … |
| 1.3.6.1.4.1.232.1.2.13.2.1.12 | cpqSePcieFunctNegotiatedLinkSpeed | 0 | 0 | This is the negotiated link speed for the PCIe link of the PCI device. An entry of 0 indicates the negotiated link speed could n… |
| 1.3.6.1.4.1.232.1.2.13.2.1.13 | cpqSePcieFunctNegotiatedLinkWidth | 0 | 0 | This is the negotiated link width for the PCIe link of the device. Value N means N lanes. An entry of 0 indicates the negotiated… |
| 1.3.6.1.4.1.232.1.2.13.2.1.14 | cpqSePcieFunctMaxLinkSpeed | 0 | 0 | This is the maximum link speed for the PCIe device. An entry of 0 indicates the maximum link speed could not be determined or th… |
| 1.3.6.1.4.1.232.1.2.13.2.1.15 | cpqSePcieFunctMaxLinkWidth | 0 | 0 | This is the maximum link width for the PCIe device. Value N means N lanes. An entry of 0 indicates the maximum link width could … |