% DPC Time is the percentage of time that the processor spent receiving
and servicing deferred procedure calls (DPCs) during the sample interval.
(DPCs are interrupts that run at a lower priority than standard interrupts).
% DPC Time is a component of % Privileged Time because DPCs are executed in
privileged mode. They are counted separately and are not a component of the
interrupt counters. This counter displays the average busy time as a
percentage of the sample time.
Parsed from file CPQWINOS.MIB.txt
Company: None
Module: CPQOS-MIB
% DPC Time is the percentage of time that the processor spent receiving
and servicing deferred procedure calls (DPCs) during the sample interval.
(DPCs are interrupts that run at a lower priority than standard interrupts).
% DPC Time is a component of % Privileged Time because DPCs are executed in
privileged mode. They are counted separately and are not a component of the
interrupt counters. This counter displays the average busy time as a
percentage of the sample time.
Parsed from file CPQOS-MIB.mib
Module: CPQOS-MIB
cpqOsCpuPercentDPCTime OBJECT-TYPE SYNTAX INTEGER ACCESS read-only STATUS mandatory DESCRIPTION "% DPC Time is the percentage of time that the processor spent receiving and servicing deferred procedure calls (DPCs) during the sample interval. (DPCs are interrupts that run at a lower priority than standard interrupts). % DPC Time is a component of % Privileged Time because DPCs are executed in privileged mode. They are counted separately and are not a component of the interrupt counters. This counter displays the average busy time as a percentage of the sample time." ::= { cpqOsProcessorEntry 10 }
Vendor: Compaq
Module: CPQOS-MIB
[Automatically extracted from oidview.com]
cpqOsCpuPercentDPCTime OBJECT-TYPE SYNTAX INTEGER ACCESS read-only STATUS mandatory DESCRIPTION "% DPC Time is the percentage of time that the processor spent receiving and servicing deferred procedure calls (DPCs) during the sample interval. (DPCs are interrupts that run at a lower priority than standard interrupts). % DPC Time is a component of % Privileged Time because DPCs are executed in privileged mode. They are counted separately and are not a component of the interrupt counters. This counter displays the average busy time as a percentage of the sample time." ::= { cpqOsProcessorEntry 10 }
| OID | Name | Sub children | Sub Nodes Total | Description |
|---|---|---|---|---|
| 1.3.6.1.4.1.232.19.2.3.2.1.1 | cpqOsCpuIndex | 0 | 0 | This Processor Instance number. |
| 1.3.6.1.4.1.232.19.2.3.2.1.2 | cpqOsCpuInstance | 0 | 0 | This Processor Instance Name. |
| 1.3.6.1.4.1.232.19.2.3.2.1.3 | cpqOsCpuInterruptsPerSec | 0 | 0 | Interrupts/sec is the average number of hardware interrupts the processor is receiving and servicing in each second. It does not… |
| 1.3.6.1.4.1.232.19.2.3.2.1.4 | cpqOsCpuTimePercent | 0 | 0 | %Processor Time is the percentage of time that the processor is executing a non-Idle thread. This counter was designed as a prim… |
| 1.3.6.1.4.1.232.19.2.3.2.1.5 | cpqOsWarCpuTimePercent | 0 | 0 | Warning alarm will be issued if, (cpqOsCpuTotalCpuTimePercent >= cpqOsWarCpuTotalCpuTimePercent && cpqOsCpuTotalCpuTimePercent < cpqOsCriCpuTotalCpuTimePercent) f… |
| 1.3.6.1.4.1.232.19.2.3.2.1.6 | cpqOsCriCpuTimePercent | 0 | 0 | Critical alarm will be issued if, (cpqOsCpuTotalCpuTimePercent >= cpqOsCriCpuTotalCpuTimePercent) for 15 data collection interval… |
| 1.3.6.1.4.1.232.19.2.3.2.1.7 | cpqOsCpuUserTimePercent | 0 | 0 | %User Time is the percentage of non-idle processor time spent in user mode. User mode is a restricted processing mode designed f… |
| 1.3.6.1.4.1.232.19.2.3.2.1.8 | cpqOsCpuPrivilegedTimePercent | 0 | 0 | %Privileged Time is the percentage of non-idle processor time spent in privileged mode. (Privileged mode is a processing mode de… |
| 1.3.6.1.4.1.232.19.2.3.2.1.9 | cpqOsCpuCondition | 0 | 0 | The condition of this Processor Object Instance. |
| 1.3.6.1.4.1.232.19.2.3.2.1.11 | cpqOsCpuPercentInterruptTime | 0 | 0 | % Interrupt Time is the percentage of time the processor spent receiving and servicing hardware interrupts during the sample int… |